\doxysubsubsubsection{RCC PLL Clock Output }
\hypertarget{group___r_c_c___p_l_l___clock___output}{}\label{group___r_c_c___p_l_l___clock___output}\index{RCC PLL Clock Output@{RCC PLL Clock Output}}
\doxysubsubsubsubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\Hypertarget{group___r_c_c___p_l_l___clock___output_gaf14f5e060d1cd0eefbdea80b8701819c}\label{group___r_c_c___p_l_l___clock___output_gaf14f5e060d1cd0eefbdea80b8701819c} 
\#define {\bfseries RCC\+\_\+\+PLL1\+\_\+\+DIVP}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVP1\+EN
\item 
\Hypertarget{group___r_c_c___p_l_l___clock___output_ga17b76fed00a13293497b825af7863d99}\label{group___r_c_c___p_l_l___clock___output_ga17b76fed00a13293497b825af7863d99} 
\#define {\bfseries RCC\+\_\+\+PLL1\+\_\+\+DIVQ}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVQ1\+EN
\item 
\Hypertarget{group___r_c_c___p_l_l___clock___output_ga2832fd9d69e723c0f667fe8f08863e0d}\label{group___r_c_c___p_l_l___clock___output_ga2832fd9d69e723c0f667fe8f08863e0d} 
\#define {\bfseries RCC\+\_\+\+PLL1\+\_\+\+DIVR}~RCC\+\_\+\+PLLCFGR\+\_\+\+DIVR1\+EN
\end{DoxyCompactItemize}


\doxysubsubsubsubsection{Detailed Description}
